1. Field of the Invention
The present invention relates to surface-channel metal-oxide semiconductor (MOS) transistors, their complementary field-effect transistors (FETs) and methods of producing them. More particularly, a surface-channel PMOS (P-channel metal-oxide semiconductor), surface-channel NMOS (N-channel metal-oxide semiconductor), dual-gate CMOS (complementary metal-oxide-semiconductor) and a method of producing the same are provided.
2. Description of Related Art
In FETs with dielectric gates employed in semiconductor integrated circuits (ICs) now in use, short-channel effects such as a decline in threshold voltage, deterioration in subthreshold characteristics and punchthrough are often seen with microminiaturization of devices since the ratio of a depletion layer charge of a gate electrode becomes smaller to the entire depletion layer charge. PMOSs, in particular, suffer from more considerable short-channel effects than NMOSs.
One reason for such short-channel effects is that boron, which has a large diffusion coefficient and a large implant range, is used as an impurity for forming source/drain regions in a PMOS.
Another reason is that a conventionally used PMOS has a gate electrode formed of the same N+ polysilicon as NMOS and a buried channel for controlling the threshold voltage. In such a construction, since the channel is formed away from the MOS surface, the control of the gate over the inversion charge density becomes weaker and therefore considerable short-channel effects are produced.
For reducing such phenomena, a surface-channel PMOS is constructed to have a P+ polysilicon gate electrode and form a pair with a conventional surface-channel NMOS. Thus the PMOS and NMOS are both of surface-channel type suitable for reducing the short-channel effects.
A CMOS having such surface-channel type NMOS and PMOS (hereafter referred to as dual-gate CMOS) will be explained with reference to figures.
As shown in FIG. 8, a P-well 2 and N-well 3 are formed in a silicon substrate 1. Formed in the P-well 2 is an NMOS transistor including a gate dielectric film 5, an N+ polysilicon gate electrode 16a, a sidewall-spacer 19, silicides 12 and 12a, source/drain regions 20 and LDD (lightly doped drain/source) regions 17. And formed in the N-well 3 is a PMOS transistor including a gate dielectric film 5, an P+ polysilicon gate electrode 16b, a sidewall-spacer 19, silicides 12 and 12a, source/drain-regions 21 and LDD regions 18.
A method of producing the dual-gate CMOS will hereafter be described.
First, as shown in FIG. 6, the P-well 2, the N-well 3 and a field dielectric film 4 are formed on the silicon substrate 1. Then, the gate dielectric film 5 and the intrinsic polysilicon gate electrodes 16 of a thickness of 200 to 300 nm are formed.
Next, as shown in FIG. 7, Nxe2x88x92 LDD regions 17 and Pxe2x88x92 LDD regions 18 are formed through lithography process and ion implantation, and the sidewall-spacer 19 is formed through a CVD process and anisotropic etching.
Then, as shown in FIG. 8, the N+ source/drain regions 20 and the P+ source/drain regions 21 are formed and the polysilicon gate electrodes 16 are doped through lithography process, ion implantation and activation annealing. Then the suicides 12 and 12a are formed on the source/drain regions and the gate electrodes through sputtering using a refractory metal as a target, selective silicidation and removal of unreacted refractory metal. In the ion implantation for the formation of the N+ source/drain regions 20 and the P+ source/drain regions 21 and for the doping of the polysilicon gate electrodes 16, 75As+ and 49BF2+ are usually used so that shallow source/drain regions can be obtained. Through the above-described processes, the dual-gate CMOS is constructed.
Alternatively, in order to reduce the short channel effects in PMOS, an N-type highly doped region 24 of an impurity concentration a little higher than that of a channel region is formed as shown in FIG. 9 after the polysilicon gate 16 is formed as shown in FIG. 6. By the N-type highly doped region 24, the extension of the depletion layer from the source/drain regions is barred and the short channel effects are reduced. Though FIG. 9 illustrates PMOS, a similar technique can be used with NMOS.
In the above-mentioned method of producing a dual-gate CMOS, 49BF2+ whose implant range is small is implanted for the formation of the source/drain regions in PMOS with a view to reducing the short channel effects, and then the activation annealing is carried out.
However, the use of 49BF2+ involves a problem that the shift of flat band voltage becomes significantly larger compared with a case where 11B+ is used. FIG. 10 illustrates plotted relations of the flat band voltage to annealing temperature when a furnace annealing or a rapid thermal annealing (RTA) is performed in various temperatures of P-substrates with gate dielectric films (the film thickness being 5 nm) and intrinsic polysilicon gate electrodes doped with 49BF2+ or 11B+. When the furnace annealing is carried out at 900xc2x0 C. for 30 minutes after the ion implantation with 49BF2+ (denoted by xe2x97xaf in FIG. 10), the flat band voltage shifts significantly. This shift of the flat band voltage indicates that boron atoms penetrate into the silicon substrate from the polysilicon gate electrode via the gate dielectric film with the furnace annealing. It is remarked that this phenomenon not only changes the flat band voltage but also leads to a decrease in dielectric immunity.
For reducing the above-mentioned shift of the flat band voltage, RTA such as lamp annealing is employed. Referring to FIG. 10, when RTA is carried out, the flat band voltage does not shift in either case with 49BF2+ or 11B+. However, RTA is not sufficient for activating the source/drain regions and reducing junction leakage, and cannot provide the same characteristics to the semiconductor as the furnace annealing provides.
Alternatively, a nitrided oxide film is used as the gate dielectric film. However, when the nitrided oxide film is formed by the use of NH3, a number of electron traps are produced by hydrogen atoms and the reliability of the device is disadvantageously lowered. When N2O is used for the nitrided oxide film, fewer electron traps are produced, but the number of nitrogen atoms which are effective against the penetration of boron atoms is smaller compared with the nitrided oxide film obtained by using NH3, so that the penetration of boron atoms into the silicon substrate can hardly be prevented.
Considering the reliability of the device, it is questionable to use 49BF2+.
Moreover 49BF2+ adversely affects not only the characteristics of MOS but also a silicided diffusion layer. FIG. 11 shows the relation of sheet resistance to an implant dose in the source/drain regions where TiSi2 is formed. When 49BF2+ is used, the sheet resistance significantly increases at high doses compared with the 11B+. This is not desirable because it increases parasitic resistance in PMOS.
In the above method of forming a dual-gate CMOS, there is another remark. Since the polysilicon gate electrode is doped by ion-implantation, the profile of the impurity in the polysilicon gate electrode (film thickness referred to as TPOLY) is like the Gaussian distribution. Therefore, the condition represented by the following formula must be satisfied:
Rp+3xcex94Rp less than TPOLY (Rp: implant range, xcex94Rp: implant diffusion) 
When the impurity is not diffused well by annealing, the concentration of the impurity does not reach 1020 cmxe2x88x923 near the interface of the polysilicon gate electrode with the gate dielectric film. This is well marked when the impurity is implanted with low energy for providing shallow source/drain regions. In such a case, since a depletion layer is produced near the interface of the polysilicon gate electrode with the gate dielectric film in a strong inversion state of a field-effect transistor, the controllability of the gate becomes weak, the short-channel effects increases, transconductance decreases, and subthreshold characteristics deteriorate. Such problems are most remarkable when the polysilicon gate electrode of NMOS is doped with As.
Therefore, although it is preferable to make the gate electrode thinner, when P+ polysilicon gate electrode in CMOS with PMOS and NMOS formed on a substrate is implanted with 11B+, boron can be doped in a concentration of 1016 cmxe2x88x923 or more into the gate dielectric film and a channel region directly under the gate dielectric film due to profile tail by channeling or the like, so that possibly a fixed charge is generated in the gate dielectric film or the concentration of the impurity in the channel is caused to change. Particularly, the above phenomenon is remarkable when the crystal structure of polysilicon gate electrode is columner. Therefore, it is difficult to make the gate electrode a thin film.
Further, although the N-type highly concentrated region 24 formed as shown in FIG. 9 reduces the extension of the depletion layer from the source/drain regions so that the short-channel effects can be reduced, the transfer conductance and subthreshold characteristics deteriorate since the impurity concentration rises near the LDD end of the channel region. Additionally, it is difficult to reduce the junction leakage and junction capacitance of periphery.
The present invention provides a surface-channel MOS transistor comprising; a gate electrode formed on a semiconductor substrate with a gate dielectric film therebetween and source/drain regions formed in the semiconductor substrate wherein the gate electrode is formed at least a polysilicon layer of a thickness of 100 to 200 nm uniformly doped with an impurity and the source/drain regions contains the same impurity in self-alignment with the gate electrode.
Further, the present invention provides a complementary FET in which a PMOS FET and NMOS FET both having the above construction are formed on the same semiconductor substrate.
Still further, the present invention provides a method of producing a surface-channel MOS transistor comprising the steps of; (i) forming a gate dielectric film on a semiconductor substrate and depositing an intrinsic polysilicon layer of a thickness of 100 to 200 nm on the gate dielectric film, followed by patterning into a desired configuration to form a gate electrode; and (ii) doping the gate electrode with an impurity by implanting an impurity from the top of the gate electrode while simultaneously source/drain regions are formed in self-alignment with the gate electrode.
According to the present invention, it provides a surface-channel PMOS having reliable device characteristics wherein the short-channel effects are reduced, an NMOS and a complementary field-effect transistor having good device characteristics wherein the generation of a depletion layer is inhibited near the interface of the gate electrode with the gate dielectric film, and a method of producing the same. In the formation of such a transistor, a relatively thin polysilicon layer can be used both in NMOS and PMOS for the gate electrode, and 11B+ instead of 49BF2+ may be used for the formation of source/drain regions and the doping of a gate electrode in PMOS.